Figure 8: Sm3 2 Pipeline-stage Plot 9 a Transistor Sizing 7 Control Path Synthesis 8 Data Path Synthesis

average peak perf./ cost average perf/cost Data path cost Performance Performance/Cost peak (1 2 2 2 3 6) (1 2 2 2 3 6) (1 2 2 2 3 6) Stages 6/6 6/5 6/4 6/3 6/2 6/1 6/6 6/5 6/4 6/3 6/2 6/1 6/6 6/5 6/4 6/3 6/2 6/1 Designs (a) (b) (c) Figure 9: Cost/Performance implemented the TDY-43, a 250 instruction processor which supports eight addressing modes. From an ISA speci cation, ADAS produced a gate-level VHDL netlist for implementation by gate array. The design also implements a JTAG standard scan testing protocol. The implementation produced by ADAS requires 34K gates or 380K transistors and has been veri ed at the gate-level using benchmark-driven test vectors. 12Conclusion In this paper, we have presented a full range microprocessor design automation system. It is demonstrated that by giving an instruction set, ADAS can automatically generate layout of a single chip microprocessor. By utilizing the benchmark simulation data, high level synthesis tools provide valuable information to guide the low level synthesis. Future research on ADAS includes further exploration of the interaction between di erent levels of design tools, capturing design knowledge for the redesign to meet constraints and extending the scope to multi-chip module (MCM) design. Acknowledgements We would like to thank Dave Boyer, Bill Bush, Angela Cheng, Rick McGeer, Dylan McNamee, Jonathan Pincus, Wes Reed, and Steve Schoetler for their contributions to this research and Paul A. Suhler for his contributions to this paper.